1. Field of the Invention
The present application relates to the field of semiconductor processing and more particularly to a method of forming isolation structures within a semiconductor substrate using an oxygen implant.
2. Description of the Relevant Art
In an integrated circuit, a plurality of semiconductor transistors are fabricated on a monolithic substrate typically comprised of a semiconductor such as silicon or gallium arsenide. The plurality of transistors are subsequently selectively coupled to one another to achieve a desired circuit. To prevent inadvertent coupling of neighboring transistors, isolation structures must be used to physically and electrically isolate each of the individual transistors. Well developed processes for isolating transistors are well known within the field of semiconductor processing. Referring to FIGS. 2a through 2f, the local oxidation of silicon (LOCOS) process is shown. In FIG. 2a semiconductor substrate 200 is provided and a pad oxide layer 202 is then formed on upper surface 201 of semiconductor substrate 200 as shown in FIG. 2b. Pad oxide 202 typically requires a dedicated processing step in which the pad oxide 202 is either grown in a thermal oxidation tube or deposited within a thin film deposition apparatus.
Silicon nitride layer 204, as shown in FIG. 2c, is then deposited upon pad oxide layer 202. Nitride layer 204 is then patterned to form a patterned nitride layer 206 as shown in FIG. 2d. Patterned nitride layer 206 is formed such that the nitride portions of the layer are aligned over first and second active regions 208a and 208b respectively of semiconductor substrate 200. The patterning of silicon nitride layer 204 is typically accomplished with a photolithography masking step and a corresponding nitride etch step. After silicon nitride layer 204 has been patterned appropriately, a thermal oxidation process represented in FIG. 2e by reference numeral 212 is performed to grow an isolation oxide 214 substantially within isolation region 210 of semiconductor substrate 200. As is well known in the field of semiconductor processing, subjecting a silicon substrate to a high temperature oxygen bearing ambient in the presence of a patterned silicon nitride mask results in the selective oxidation of the silicon surface in those regions of the silicon substrate where the silicon nitride has been removed. It is also well known that thermal oxidation of silicon characteristically results in a first portion of the oxide being contained below the upper surface of the original silicon substrate while a second portion of the resulting oxide is formed above the original surface of the silicon substrate. Typically, the oxidation process required to grow isolation oxide 214 requires subjecting silicon substrate to a heated ambient for a duration typically in excess of 60 minutes. This comparatively long thermal oxidation process consumes valuable resources of the fabrication facility for extended periods of time. In addition, the local oxidation process is well known for producing "birds beak" structures 216 at the lateral edges of the isolation oxide 214. The birds beak structures 216 undesirably encroach upon active regions 208a and 208b of silicon substrate 200 thereby reducing the maximum obtainable transistor density. After formation of isolation oxide 214, patterned nitride mask 206 is typically stripped from the wafer resulting in the partial cross-sectional view shown in FIG. 2f. In addition to the problems characteristic of the LOCOS process noted above, the LOCOS process results in a non-planar upper surface 215 defined by upper surface 201 of semiconductor substrate 200 and the upper surface of isolation oxide 214. Non-planar surfaces are undesirable because they tend to increase the difficulty of manufacturing subsequent layers of the integrated circuit. Photolithography steps, for example, are limited by the depth of field of the photolithography equipment. Exposing a non-planar photoresist layer may result in unwanted line width variation in the regions of non-planarity.
In an attempt to eliminate the long oxidation process required by the LOCOS method and to address the undesirably non-planar surface that results from the LOCOS process, semiconductor manufacturers have typically turned to shallow trench isolation (STI) isolation processes as shown in FIGS. 1a through 1e. FIG. 1a shows semiconductor substrate 100. Semiconductor substrate 100 includes an isolation region 104 laterally displaced between first and second active regions 102a and 102b. In FIG. 1b, an isolation trench 106 is etched into isolation region 104 of semiconductor substrate 100. The isolation trench process is preceded by a photoresist masking step that permits the selective etching of portions of semiconductor substrate 100 within isolation region 104. Care must be taken during the formation of isolation trench 106 to ensure that the trench sidewalls are substantially vertical to minimize the encroachment of isolation trench 106 into active regions 102a and 102b of semiconductor substrate 100. In addition, conventional etch technology places an upper limit on the aspect ratio of isolation trench 106. The aspect ratio refers to the ratio of the trench depth d to the trench width w. Typically, trenches with aspect ratios greater than approximately 1 are more difficult to fabricate than trenches with aspect ratios less than 1. This constraint places an upper limit on the depth d or, alternatively, a lower limit on the width w of isolation trench 106. Both of these constraints are undesirable as deeper trenches are preferred to shallow trenches because deeper trenches result in more effective isolation between adjacent active regions while narrower trenches are preferred because they permit higher density transistor formation.
Turning now to FIG. 1c, a thin thermal oxide 108 is typically grown after the formation of isolation trench 106 to place a thermal oxide layer at the sidewalls and floor of isolation trench 106. The formation of thermal dielectric 108 is believed to result in a more reliable isolation structure, but requires a dedicated thermal oxidation process. Turning to FIG. 1d, a trench dielectric layer 110 is typically deposited over the topography defined by semiconductor substrate 100 and isolation trench 106. The deposition of trench dielectric layer 110 is typically accomplished by a dedicated thin film deposition process. Subsequently, a planarization process is typically required to remove portions of trench dielectric layer 110 exterior to isolation trench 106. The complete planarization of trench dielectric 110 may require multiple processing steps including one or more chemical mechanical polish steps possibly in combination with one or more photolithography masking steps and wet or dry etch steps. FIG. 1e shows an idealized shallow trench isolation structure 114 laterally situated between a pair of active regions 102a and 102b of a semiconductor substrate 100. It will be appreciated to those skilled in the art that the shallow trench isolation process addresses the long oxidation cycle required by LOCOS processing and generally produces a more planar upper surface than is possible with the LOCOS. Nevertheless, the shallow isolation process requires a dedicated isolation etch step, a thermal oxidation step, a thin film deposition step, and one or more planarization steps. As noted previously, the geometry of the shallow trench isolation structure itself is typically limited by the capabilities of the etch process. In summary, the shallow trench isolation process offers advantages over the LOCOS isolation process but, nevertheless, includes significant processing overhead and may inherently possess process limitations that could prove to be significant as the geometries of isolation structures are reduced.
It is therefore desirable to implement an isolation process which significantly reduces the amount of processing overhead and expense typically required of conventional isolation processes. In addition, it is desirable to utilize an isolation process free of the geometric constraints imposed by LOCOS and STI process flows.